MOSFET gate charge is the parameter to design a driver around, because the input capacitance figure on a datasheet changes dramatically with the voltages applied and is nearly useless for calculating anything. Charge tells you how much the driver must deliver to switch the device, and dividing it by the time you allow gives the current the driver must supply.
Why capacitance is a misleading number here
The capacitances inside a MOSFET are formed by depletion regions whose width varies with the applied voltage, so they are strongly nonlinear. The gate-drain capacitance in particular can change by more than an order of magnitude across the drain voltage range, being largest when the drain voltage is low. A single input capacitance figure quoted at one bias point therefore fails to describe what the driver experiences during a real switching transition, where the drain voltage sweeps across its whole range. Gate charge measurements sidestep the problem entirely by integrating the actual charge delivered under a defined switching condition, producing numbers that can be used directly for driver sizing and loss estimation.
Reading the gate charge curve
The characteristic plot shows gate-source voltage against charge delivered and has three distinguishable regions. The first is a rising section as the gate-source capacitance charges toward the threshold and beyond. The second is a flat plateau, sometimes called the Miller plateau, where the gate voltage barely changes while charge continues to flow, because the drain voltage is swinging and the charge is going into the gate-drain capacitance. The third is a further rise as the gate is driven to its final voltage, reducing on-resistance. The plateau is the important region: it is where the device is simultaneously carrying current and supporting voltage, which is where switching loss occurs, and its length in charge determines how long that overlap lasts for a given drive current.
Turning charge into driver requirements
Driver peak current is the charge divided by the time available, so a device with a large plateau charge switched quickly demands a driver capable of amperes even though the average gate current is small. The driver must supply that current through its own output impedance and through any external gate resistor, and the resulting effective resistance sets the achievable switching speed. Average driver power is the total gate charge multiplied by the drive voltage and the switching frequency, and at high frequency this becomes a significant dissipation in the driver itself. Gate charge also explains why a device with lower on-resistance is not automatically better: larger die area lowers conduction loss and raises gate charge, so the best choice depends on where your operating point sits between conduction-dominated and switching-dominated.
Faster switching is not always the goal
Reducing the gate resistance shortens the overlap and cuts switching loss, which is attractive until the consequences appear elsewhere. Faster edges increase ringing with circuit parasitics, raise electromagnetic emissions, and can push the switch node beyond safe voltages. In a half bridge, fast switching of one device can couple through the other’s gate-drain capacitance and partially turn it on, a failure known as induced turn-on that causes shoot-through and can destroy both devices. Remedies include a negative or actively clamped off-state gate voltage, separate turn-on and turn-off resistors so the device turns off faster than it turns on, and a low-impedance gate path. Gate resistance is therefore a deliberate compromise between loss, noise and safety rather than a value to minimize.
Verifying on real hardware
Measure the gate-source voltage with a short-ground probe at the device pins and look for the plateau, whose duration tells you the real switching time in your circuit rather than in the datasheet’s test fixture. Watch for any bump in the off-state gate voltage when the opposite device switches, which is the signature of induced turn-on. Observe the switch node for overshoot and ringing, and check device temperatures to see whether conduction or switching loss dominates by varying frequency at constant current. All of this requires probing technique appropriate to the speeds involved, and in mains-referenced or high-voltage circuits it requires isolation and safe work practices, since the gate reference may be floating at a hazardous potential.
What to check before you act
- Size the driver from gate charge divided by the transition time you need.
- Budget driver dissipation as total charge times drive voltage times frequency.
- Use separate turn-on and turn-off resistors where induced turn-on is a risk.
- Probe the gate at the device pins with a short ground connection.
Common questions
Why does my gate voltage flatten partway through the transition?
That plateau is the interval when the drain voltage is swinging and charge is flowing into the gate-drain capacitance. It is normal and marks where switching loss is generated.
Should I always use the smallest gate resistor possible?
No. Faster edges reduce switching loss but increase ringing, emissions and the risk of induced turn-on in a bridge. Choose the value from measured behavior, not from loss alone.
The practical takeaway
Design gate drive from charge rather than capacitance, size the driver for the peak current the plateau demands, and treat gate resistance as a compromise you tune on hardware. Confirm the transition with a properly grounded probe at the device pins, using isolation and safe practices wherever the circuit is referenced to a hazardous potential.
References and further reading
- Department of Energy: how electronics losses turn into wasted energy and heat
- FCC: electromagnetic compatibility and radio frequency safety questions answered
- CDC NIOSH: electrical safety fundamentals for anyone working on powered equipment
Numerical scenarios are illustrative unless identified otherwise. Follow the exact product instructions; component ratings and local installation requirements can differ.
